Controlling Return Current Paths In Multi-Layer Pcbs
What are Return Current Paths and Why Control Them?
Return current paths refer to the routes that return currents take through reference planes back to their source. As high-speed signals propagate along traces in a PCB, equal but opposite return currents flow back through the ground or power planes. These return current paths are critical for maintaining signal integrity and controlling EMI. If the return path is disrupted, it can cause large loop areas that introduce excessive inductance, leading to phenomena like ground bounce, signal degradation, and crosstalk. Therefore, it is essential to strategically control return current paths in multi-layer PCBs to mitigate these issues.
Strategies for Controlling Return Current Paths
Use entire ground plane layers
Using dedicated, uninterrupted ground plane layers provides an ideal low-impedance return path directly below critical traces. The ground planes should be sufficiently large to accommodate return current flows underneath traces. Splitting ground planes should be avoided underneath active circuitry to maintain continuous return paths.
Minimize splits in ground planes
Sometimes it is necessary to split ground planes, such as for sensitive analog circuitry or isolating noise. However, excess splitting can force return currents to take long detours, increasing inductance. Therefore, keep the number and area of splits to the minimum size necessary, and avoid splitting under critical high-speed paths.
Use stitching vias around traces
Stitching vias help bridge gaps in return planes near splits or planes changes under traces. The vias provide a direct vertical return path between planes, shunting return currents across gaps that would otherwise force longer detoured horizontal return paths. A via fence or array of stitching vias around traces helps mitigate this.
Optimize component placement
Carefully placing terminating resistors, decoupling capacitors, and other components can help maintain localized return current loops near sources. Low-inductance surface-mount packaging is ideal. Ensure space for routing return vias next to traces.
Routing Differential Pairs
Length matching
The two conductors in a differential pair should be routed with identical matched lengths to ensure signals arrive simultaneously. Length mismatches lead to skew between the positive and negative waveforms, reducing noise cancelling benefits of differential signals.
Spacing pairs correctly
Ideal spacing between the two conductors of a differential pair balances minimizing crosstalk between other signals, and minimizing differential impedance mismatches along the line. Wider spacing reduces odd-mode impedance but increases loop area, while tighter spacing raises odd-mode impedance but lowers loop area.
Symmetry of vias
Any vias in each conductor of a differential pair should be symmetrically arranged to maintain uniform coupling and identical path lengths. The vias in each line being directly opposite balances electrical length, minimizes skew, and provides uniform return current paths.
Simulating Return Current Paths
Overview of field solvers
Advanced field solver EDA tools like Ansys HFSS can simulate current flows and model ground plane impedances seen by signals. These can provide insight into actual return current paths taken based on a particular PCB stackup and trace layout before manufacturing the board.
Example simulations
An example practical use would be modeling currents near an irregular split in the ground plane under a high-speed data path to visualize any unexpected return path detours indicating excessive shared current loops that may require mitigation.
Mitigating Issues
Fixing return path problems post-layout
If post-layout signal integrity simulations or measurements indicate excessive noise or emissions due to disrupted return current paths, fixes like bridging ground plane splits with cross-hatched copper pours can redirect return path flows.
Bandage fixes like adding capacitors
Carefully placed bypass capacitors can provide localized AC current returns between power and ground planes, reducing shared loop areas. However, this band-aids rather than addresses root cause, as best practice is optimizing the inherent ground plane return paths pre-layout.
Conclusion
Summary of techniques
In summary, best practices for controlling return current paths include using robust ground planes, minimizing splits under traces, strategic stitching vias, optimum component placement, matched differential pairs, and pre-layout modeling. This helps maintain signal quality and contained EMI across complex multi-layer PCBs.
Importance of planning for return currents early in design process
As high-density PCBs push towards higher speeds and lower emissions, considering return current paths early when planning stackups and layout is essential to build in robust SI and EMI control from the start.
