Design Considerations For Power Supply Decoupling Capacitors

Decoupling Capacitor Fundamentals

What is a Decoupling Capacitor and Why is it Needed?

A decoupling capacitor is a capacitor used to decouple one part of an electrical network from another. Decoupling capacitors are used to filter noise, minimize voltage droop, and store charge for integrated circuits (ICs), helping stabilize power distribution. They are essential components in modern printed circuit board (PCB) design. Without proper decoupling, ICs can experience temporary brownout events, clock jitter, increased electromagnetic interference (EMI), and other issues that compromise functionality or reliability.

Decoupling Capacitor Functions: Bypassing, Filtering, Storing Charge

Decoupling capacitors have three core functions:

• Bypassing – They act as a local charge reservoir, providing current to an IC when demand temporarily exceeds supply capability.
• Filtering – They short higher frequency noise to ground, preventing propagation through power distribution networks.
• Charge Storage – They minimize voltage droop at IC power pins by supplying current during sudden demands.

These functions work together to deliver clean, stable voltage to sensitive circuitry.

Decoupling Capacitor Placement Considerations

Strategic placement of decoupling capacitors is crucial for their effectiveness. Guidelines include:

• Mount decoupling capacitors as close as possible to power pins of targeted ICs, minimizing parasitic inductance.
• When forced to choose, favor decoupling capacitor proximity over trace considerations.
• Use separate VDD and VSS vias for each decoupling capacitor to provide dedicated returns.
• Duplicate decoupling arrays across symmetrical planes on multilayer boards for enhanced noise suppression.

Following these placement strategies reduces power distribution impedance most effectively.

Choosing the Right Decoupling Capacitance

Selecting appropriate target values for decoupling capacitance requires assessing needs of specific ICs along with board-level considerations:

• Review IC datasheets – Many recommend target decoupling levels per supply pin.
• Understand IC operating modes – Peak current draw dictates charge needed from local decoupling.
• Consider intended clock speeds – Higher frequencies demand lower impedance decoupling networks.
• Analyze board-level power distribution – Impedance targets drive decoupling requirements.
• Model transient load behavior – Simulate or measure to quantify decoupling needs.

Tailoring decoupling capacitance levels and mix to the application and actual load requirements leads to optimized implementation.

Equivalent Series Inductance and Resistance

Equivalent series inductance (ESL) and resistance (ESR) are critical decoupling capacitor parameters. Minimizing them helps achieve:

• Lower impedance across wider frequency range
• Reduced voltage droop from sudden load changes
• Maximized bypassing and filtering performance

multi-capacitor configurations leverage complementary characteristics to minimize overall ESL and ESR. Mounting style and parasitics must also be considered during capacitor selection.

Types of Decoupling Capacitors: Ceramic, Tantalum, Polymer, Electrolytic

Ceramic Capacitors

Low cost option with excellent high frequency characteristics. Values up to 100 μF are practical. Drawbacks are lower capacitance per volume than other technologies and potential piezoelectric effects. Dielectric types include X7R, X5R and hi-K. Common case sizes from 0402 to 2220.

Tantalum Capacitors

Provide very high capacitance per volume. More costly than ceramic but useful for intermediate frequencies. Vulnerable to damage from current spikes if not properly derated. Case sizes from A to D most typical.

Polymer Capacitors

Offer ultra-low ESR and stable temperature characteristics. Penalty is lower overall capacitance than other options. Can replace multiple ceramic capacitors. Often used for processor decoupling arrays where reliability is critical.

Aluminum Electrolytic Capacitors

Highest capacitance per volume makes them useful for bulk decoupling applications. Only suitable for lower frequencies due to higher ESR. Larger case dimensions than other types results in higher parasitic inductance as well.

Selecting the proper mix achieves maximized performance across wide frequency and load ranges.

Simulating and Measuring Decoupling Effectiveness

Simulation

Modeling decoupling networks with SPICE or dedicated SI/PI tools allows optimization early in the design flow. Critical specifications like target impedance, allowable voltage ripple, transient response and more can be defined, facilitating required capacitor mix selection and placement.

Measurement

Once prototypes are available, the most direct assessment method is to inject noise or pulses into the power rails while directly observing IC supply pin voltage. Comparison to specified thresholds validates performance. Other tests like scan chain errors, eye diagrams, jitter analysis, and radiated emissions provide indirect decoupling evaluation. Optimization is achieved by iteratively adjusting decoupling networks based on measured results.

Combining simulation early for informed starting points with empirical validation and refinement leads to robust implementations able to handle worst case conditions.

Decoupling Capacitor Guidelines by IC Type

Microprocessors

Use arrays with 8-10 capacitors featuring 1μF to 100μF range. Include ceramic, polymer, tantalum types. Separate Vcore and I/O rail decoupling. Place pairs at each bump/land exiting package.

DSP/FPGA/ASICs

Similar to microprocessors but also add moderate value ceramic capacitors adjacent to each supply pin. 100nF is typical. Support special voltage rails like PLL/analog.

Memory ICs

Smaller decoupling arrays featuring 10nF-1μF ceramic capacitors, clustered near DQ/DQS pins. Each voltage entry point to IC needs 1μF+ decoupling. Add tantalum bulk capacitance to cover multi-device load peaks.

Voltage Regulators

Input and output decoupling mandatory. Support recommended levels in device datasheets. Values from 10μF to 470μF are typical. Use low ESR polymer electrolytic or tantalum to handle potential load spikes.

These provide general guidelines but device-specific decoupling advice supersedes as required to handle maximum transient loads per published specifications.

Example Decoupling Schematics for Common ICs

16-Bit Microcontroller Decoupling

This schematic shows best-practice board-level power distribution and decoupling for a typical 16-bit microcontroller. Key points:

• Ferrite bead isolate digital core from other loads
• Direct bond copper plane for low inductance
• 4 capacitor types to complement characteristics
• Each supply rail has distinct decoupling array
• Regulator uses dedicated input/output capacitors

Proper schematic-level partitioning combined with robust decoupling and power supply integration prevents cross contamination of analog and digital sections while delivering clean stable voltage to the IC core.

Quad-Channel DDR4 Memory Decoupling

This DDR4 memory schematic highlights key concepts:

• Individual capacitor decoupling at each supply point
• Direct vias underneath the IC connected to internal planes
• Careful routing of traces to reference planes
• Additional capacitor banks on data bus for transient loads
• Uniform distribution for symmetrical approach angles

Applying these guidelines yields excellent stability in demanding memory applications with fast edge rates.

Troubleshooting Insufficient Decoupling

Defining objective pass/fail metrics first facilitates methodical debugging:

• Set specific line or load regulation limits per datasheets
• Quantify max acceptable voltage droop or ringing
• Establish target impedance profiles from simulations
• Catalog other suspected failure modes like increased jitter or emissions

Armed with clear measurable criteria, systematically adjust design variables:

• Increase decoupling values/types for more charge reserves
• Re-position capacitors closer to IC pins to cut inductance
• Dedicate additional power/return vias for lower impedance
• Review routing for antigenic loops or discontinuities
• Consider modifying layer stack and planes

Repeating measurements as changes are made rapidly exposes sensitivity to each parameter – guiding design improvements targeting the dominant factors.