Emerging Challenges In Smps Design Due To Increased Adoption Of Gfci/Afci Breakers

Increased adoption of GFCI/AFCI breakers

The increased adoption of ground fault circuit interrupter (GFCI) and arc fault circuit interrupter (AFCI) breakers in residential and commercial buildings has introduced new design challenges for switch mode power supply (SMPS) engineers. GFCI/AFCI breakers are intended to prevent electric shocks and arc faults, but can be prone to “nuisance tripping” when used with SMPS loads that produce high frequency noise.

Expanding safety codes and standards

Safety standards like UL 943 and NFPA 70 (NEC) now require GFCI or AFCI protection on an expanding set of branch circuits. For example, NEC 210.12 requires AFCI protection on branch circuits supplying outlets in dwelling units. As these requirements expand, GFCI/AFCI breaker adoption increases.

Increased noise susceptibility

Unlike linear power supplies, switch mode power supplies inherently produce high frequency noise due the rapid switching of power semiconductors. This increases the risk of nuisance tripping with GFCI/AFCI breakers. SMPS engineers must now design with GFCI/AFCI compatibility in mind.

How GFCI/AFCI breakers detect faults

To understand the tripping issues, we must first understand how GFCI/AFCI breakers work to detect ground faults and arc faults.

GFCI Operation Basics

GFCIs function by measuring the current difference between hot and neutral lines. Under normal conditions, the currents should be equal. A ground fault occurs when some of the hot current is diverted to ground, resulting in an imbalance of 1mA to 30mA. The GFCI detects this imbalance and trips to remove voltage and interrupt the fault current path.

AFCI Operation Basics

AFCIs monitor high frequency noise signatures on the circuit to identify hazardous arcing conditions. Unintended arcs can occur due to worn outlet contacts or damaged wire insulation. The AFCI recognizes the unique noise fingerprint of arcs and interrupts power when dangerous conditions are present.

Common mode noise coupling in SMPS designs

SMPS circuits inherently produce common mode noise voltages due their switching behavior. This noise can couple to nearby conductors through stray capacitance leading to small leakage currents that can mimic faults and trigger GFCI/AFCI breakers.

Switch node ringing

Ringing occurs at the switch node of power switches during switching transitions due to resonances between transistor capacitances and stray inductances. This creates high dv/dt noise which can couple from drains of devices like FETs into adjacent traces and heatsinks connected to safety grounds.

Y capacitor discharge currents

Y-capacitors connected from the primary side circuits to safety grounds divert common mode noise away from the isolated secondary outputs. Noise currents in these capacitors can also flow through ground leads, causing imbalance on the line side.

Trace coupling

High dv/dt traces from the switch node or drain nodes can capacitively couple into adjacent low voltage control traces connected to microcontrollers, creating unintended return current paths.

Heatsink coupling

Common mode noise currents often flow to earth ground through heatsink parasitic capacitances. This can allow noise to bypass sensing circuitry and directly imbalance line currents.

Mitigation techniques

SMPS engineers have several techniques available to them to design GFCI/AFCI compatible power supplies…

Improved PCB layout

Careful attention must be given to the PCB layout to route critical high dv/dt traces away from sensitive traces and ground planes tied to earth ground. Guard rings and ground screens may also be used judiciously.

Common mode filtering

Common mode chokes blocks noise currents from exiting cables while allowing differential mode currents to pass. Common mode capacitors shunts noise currents to primary side return paths instead of ground.

Reduction of high frequency leakage

Additional line filters better containnoise within the power supply enclosure. Any unintentional chassis leakages pathways should be eliminated in the design.

Careful component selection

Opto-isolators and bias winding “core and coil” flyback designs better contain noise currents and prevent ground leakage compared to auxiliary power windings.

Adding neutral line resistor

Adding resistance in the PE line on AC side helps contain leakage by forcing it to flow back through neutral instead of ground.

Testing for GFCI/AFCI compatibility

To confirm compatibility, SMPS designs should be thoroughly tested with both GFCI and AFCI receptacles under maximum load conditions…

GFCI Testing Procedure

1. Connect DUT to GFCI receptacle outlet
2. Power on and operate at max load
3. Verify GFCI does not trip for an extended period >5 mins
4. Inject a small 30mA ground fault using resistor
5. Verify GFCI successfully detects and trips

AFCI Testing Procedure

1. Connect DUT to AFCI breaker outlet
2. Power on and operate at max load
3. Verify AFCI does not trip over long term period >24 hrs
4. Inject small series arc fault on line side wiring
5. Verify AFCI successfully detects and trips

Example circuit showing common mode noise reduction

Below is an example flyback SMPS circuit before and after common mode noise reduction modifications to prevent GFCI/AFCI tripping…

Unmodified Circuit

This basic flyback converter uses a simple auxiliary power winding on the transformer to deliver bias for the PWM controller. High frequency common mode noise can couple directly through transformer inter-winding capacitance to bypass the ground fault detection circuitry.

Modified Circuit

In the improved circuit, an external bias winding “core and coil” flyback design is used to better contain switching noise currents. Additionally, common mode choke, X caps, and neutral line resistance added to further limit ground leakage.