Examining The Internal Asymmetry Of Mosfets And Its Impact On Circuit Design
Understanding MOSFET Asymmetry
Metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamental building blocks of modern integrated circuits. However, inherent asymmetry in the structure and operation of MOSFET devices can lead to significant variability in transistor characteristics.
Defining asymmetry in MOSFETs
Asymmetry refers to a lack of symmetry in the current-voltage characteristics between the drain and source terminals of a MOSFET. This is primarily caused by microscopic variation in dopant concentrations and gate oxide thickness across the transistor area that occurs during fabrication.
Explaining threshold voltage variation
One major consequence of MOSFET asymmetry is variability in the threshold voltage (VT) – the minimum gate voltage required to create a conduction channel. Threshold voltage dictates switching timing and leakage power. Analysis shows threshold voltage variation follows a gaussian distribution across a wafer, ranging 20-30 mV for a 180 nm process.
Drain-induced barrier lowering effects
In addition, asymmetry causes the threshold voltage to be modulated by the drain voltage, an effect called drain-induced barrier lowering (DIBL). At higher drain biases, depletion regions expand and reduce the potential barrier controlling the channel. This alters turn-on characteristics each time a transistor switches.
Consequences for transistor switching
Due to asymmetry-induced parameter variations mentioned above, the switching behavior of transistors can vary significantly from ideal square law theory. This is detrimental for digital logic gates and SRAM memory cells, where uniform switching is needed for reliable operation.
Quantifying and Modeling MOSFET Asymmetry
To understand the impact of asymmetry on circuit performance, engineers rely on modeling techniques spanning from simplified static models to complex dynamic simulations.
Static modeling approaches
Static models approximate the effect of asymmetry by representing variability with independent random variables for parameters like VT and channel length. Statistical models can compactly capture distributions, correlations, and spatial gradients across a die. However, they cannot predict dynamical interactions.
Dynamic modeling approaches
In contrast, physics-based TCAD simulations use finite element methods and directly model variability sources like random dopants and line edge roughness. They can provide dynamic insights but require long run times. Parallel cluster computing is often needed for statistical analysis.
Sample model code and simulations
A sample Python code implementing a threshold voltage variation model with 30 mV sigma is shown below. Running Monte Carlo analyses on this model shows the circuit failure rate increasing from 0.1% to 5% over 200 runs, indicating how asymmetry impacts yield:
import random
import numpy as np
mean_vt = 0.5 # Volts
std_dev_vt = 0.03 # 30 mV sigma
def gen_vt():
return random.normalvariate(mean_vt, std_dev_vt)
fail_count = 0
for i in range(200):
vt = gen_vt()
if vt > 0.6 or vt < 0.4:
fail_count += 1
print(f'{fail_count/200:%} failure rate')
Circuit Impacts and Compensation Techniques
Within circuits, the asymmetry of transistors manifests in two primary ways - increased leakage and altered switching speeds.
Increased leakage current
Due to threshold voltage variation, some transistors will have significantly lower thresholds and conduct higher off-state leakage current. Leakage can account for 30-50% of total chip power in modern process nodes.
Timing errors
Asymmetry also leads to timing errors by skewing the propagation delays along different logic paths. In synchronous circuits, this causes violations of setup and hold time constraints. Timing errors severely impact peak operating frequency.
Compensation with body-biasing
To mitigate asymmetry effects, body-biasing techniques modulate VT by applying a reverse bias voltage to the transistor bulk node. This helps balance timing delays across critical paths. Adaptive body-biasing uses on-chip monitoring and DC-DC converters.
Sizing transistors appropriately
Up-sizing transistors along timing-critical and high-fanout paths also helps compensate. However, increased parasitics can become detrimental. Careful analysis helps choose optimal sizing strategies.
Asymmetric MOSFETs in Circuit Applications
Despite challenges, asymmetry issues have not precluded MOSFETs from powering an enormous range of vital electronics applications.
Analog circuits
For analog ICs like op-amps, asymmetry directly impacts offset voltages and common-mode rejection ratios. Chopping and auto-zeroing techniques help minimize these errors.
Digital logic
In digital logic gates, keepers and skewing cell rise/fall times balance degradation from variability-induced delays. Logic families like Differential Cascode Voltage Switch help mitigate asymmetry.
Memory and storage
SRAM arrays use advanced layout, redundancy, and self-repair mechanisms to limit disturbs and stabilize yields. In flash memory, strict error correction coding handles retention failures from cell asymmetry.
Example circuit diagrams
Shown below is a self-cascode amplifier circuit optimized for fast recovery times by cancelling out asymmetry effects on slew rates and phase margins:
Future Outlook on MOSFET Symmetry
Despite ongoing efforts, manufacturing processes cannot eliminate asymmetry entirely. New perspectives target co-design of technology and system architecture.
Improved fabrication processes
Evolution to 5 nm nodes and beyond brings conformal deposition, EUV lithography, and selective doping to minimize variability during fabrication. However, randomness still persists at the atomic scale.
Adaptive body-biasing
Online monitoring and adaptive compensation techniques can provide self-healing capabilities. Asynchronous digital logic helps accommodate variability intrinsically.
Self-compensating circuit designs
Circuit architectures like differential signaling and noise-tolerant latches circumvent absolute reliance on symmetric operation. Co-design methodologies optimize the device/circuit interface for intrinsic robustness.
