Minimizing Power Consumption In Bidirectional Voltage Level Shifters
Lowering Static Power Drain
Static power drainage can account for over 50% of total power consumption in bidirectional voltage translation circuits. By carefully selecting low-power transistor architectures and utilizing sleep modes, static power can be dramatically reduced.
Using low-power transistor architectures
Power-optimized CMOS processes offer transistor variants with lower leakage compared to standard cells. For example, high-threshold transistors exhibit a high source-to-gate voltage barrier, preventing subthreshold conduction when the gates are not actively driven. Up to 30% reduction in leakage is possible by substituting high-VT devices into latch arrays and other static circuitry.
Transistors with multi-gate morphologies, such finFET and tri-gate structures, demonstrate significantly lower off-state currents due to superior electrostatic control over the channel. Bidirectional level shifters constructed with multi-gate FETs slashes static leakage by over 40% compared to traditional planar CMOS processes.
Minimizing leakage with sleep modes
Actively power gating domains when voltage translation is not required can eliminate static currents. This is commonly accomplished with header/footer sleep transistors or more advanced cluster-based power gating methodology.
Header/footer sleep transistors are integrated to gate power to the level translation circuitry itself. On supported processes, the sleep transistors exhibit special leakage-optimized characteristics. Cutting off the power rail essentially halts all static drainage. Re-enabling the header/footer transistors when bidirectional signaling is necessitated incurs some minor delay and switching overhead.
At advanced nodes, cluster-based power gating partitions the level shifter into separately controllable domains, allowing only the active partitioning to remain powered while the rest slumber. This requires extra logic to dynamically reactivate/deactivate domains but reduces sleep mode latency compared to header/footer approaches.
Optimizing Switching Power
While leakage accounts for a considerable fraction, active stepping of voltage rails during state changes continues to represent significant power expenditures. Various techniques exist to minimize unnecessary voltage transitions.
Reducing unnecessary state changes
Glitch generation on control signals can spur spurious intermediate voltage node toggling, costing energy without purpose. This wastage intensifies in mature process nodes where wire delays dominate gate propagation times. Integrating edge-rate controls, hazard mitigation, and other noise-quieting methods curtails harmful glitches.
Latches and flip-flops controlling power mode sequencing should be explicitly designed for glitch-free behavior with master-slave architectures and adjusted for balanced rise/fall times. This ensures no half-clock anomalies trigger unintended power mode transitions.
Employing efficient drive strength scaling
Superfluous overdrive of gate capacitances dissipates excess power across non-critical timing paths. Optimally tuning drive strengths to precisely satisfy transition time targets, rather than conservatively oversizing as per usual synthesis, promotes power economy.
High-fanout nets spanning multiple voltage domains are particularly subject to excess loading. Limiting fanout through insertion of regional buffers, sized precisely to regional capacitance, avoids gross overdrive from an upstream oversized gate attempting to muscle the entire net.
Example Code for Low-Power Bidirectional Level Shifter
The following executable reference design demonstrates integrated application of the aforementioned low-power techniques for minimized power bidirectional level-shifting between 1.8V and 3.3V domains.
Header files and libraries
Configuration of process-specific low-leakage high-VT cells and multi-Vt compilers occurs upfront. Glitch filtering modules are imported alongside power gating control modules.
Initializing pins and peripherals
Primary control pins are instantiated with configured slew rates and timing margins to prevent glitching. The bidirectional core domain along with separate output stages are assigned to independently power-gateable partitions.
ISR for handling power modes
Interrupt handler code issues the appropriate sleep/wake signals to the header/footer transistors depending on bidirectional translation requirements detected by upper level logic.
Core translation functions
Lean strength-sized buffer trees shift inputs from 1.8V up to 3.3V and conversely down-convert 3.3V inputs to 1.8v signals. Auto-gating of unused directional resources minimizes lingering powered-on leakage.
Further Recommendations
While the above methodology realizes substantial power savings through optimization of the level translation circuitry itself, additional benefits can be obtained by considering system-level enhancements.
Leveraging hardware acceleration
Hardware accelerators with level shifting integrated directly into I/O blocks can offload bidirectional signaling tasks from the main application processor. This avoids expending costly software routines and CPU processing overhead just to handle basic voltage translation.
Considering alternate bus interfaces
Emerging bus standards implement bidirectional translation intrinsically within the physical layer specification. Examples include SLIMbus and SerDes-based interfaces. Adopting such architectures obviates the need for explicit external level shifting entirely.
