Mitigating Parasitic Inductance And Resonance In Decoupling Capacitor Networks
Understanding Parasitic Inductance
All conductors exhibit self-inductance, which opposes changes in current flow. In decoupling capacitors, the traces, vias, and plates inside the capacitor package contribute parasitic inductance. This parasitic inductance appears in series with the capacitance, forming an unwanted LC circuit.
Parasitic inductance originates from the magnetic fields created by current flowing through metal conductors. Changing current induces loop voltages according to Faraday’s law of induction. Narrow traces and vias exhibit more parasitic inductance due to larger loop areas for magnetic flux.
In decoupling capacitors, loop inductance arises from supply and ground loops connecting the capacitor. Lead frame inductance comes from current flow through the capacitor plates and terminations. Via inductance connects the capacitor to the PCB pads, while trace inductance connects the PCB landing pads.
Impacts of Parasitic Inductance on Capacitor Performance
The impedance of a real-world capacitor depends on parasitic inductance as well as capacitance. At frequencies where inductive reactance equals capacitive reactance, the impedance starts rising, reducing decoupling effectiveness.
With higher parasitic inductance, the unwanted LC resonance occurs at lower frequencies. Large voltage spikes can develop across the inductance when current changes rapidly. The capacitor fails to shunt high-frequency noise to ground.
Controlling parasitic inductance is key to maintaining low impedance across a wide frequency band. Decoupling networks must provide consistently low impedance even over multiple decades of frequency to handle modern fast IC switching noise.
Techniques to Minimize Parasitic Inductance
Minimizing Loop Area
Since loop area controls parasitic inductance, layout techniques that minimize area also reduce inductance. Short wide traces exhibit less inductance, so capacitors should connect to adjacent ground and power planes with multiple vias.
Loop inductance combines inductors in series and parallel. Connecting capacitors directly between planes reduces loop area. But planes have some inductance, limiting performance at high frequencies.
Interleaving Multiple Vias
Using two or more vias in parallel reduces inductance since loop area decreases. Inductors in parallel combine inversely according to area. Spreading vias apart helps minimize interaction between via currents.
However, via placement requires care to route return currents correctly. Too much separation allows plane inductance to dominate. Optimal via placement depends on capacitor size and plane construction.
Using Low Inductance Capacitors
Component manufacturers produce capacitors with low equivalent series inductance (ESL). These capacitors minimize internal loop areas within the package to reduce parasitic inductance.
Low ESL capacitors feature shorter plate lengths, smaller termination areas, and direct connections to multiple vias. Common low ESL capacitor families include laminate ceramic chip capacitors and interdigitated designs.
Placement Strategies
Distributed placement surrounds ICs with many low-value decoupling capacitors. This provides local charge reservoirs that handle transient current spikes.
Further away from ICs, higher value bulk capacitors filter lower frequency noise. Mixing capacitance values prevents impedance peaks across a wide frequency range for robust supply integrity.
Software tools can automate optimized placement, routing vias to tie capacitors directly between power and ground planes. Eliminating trace inductance where possible improves high frequency decoupling.
Example Code for Optimized Placement
/* Load netlist */
netlist = read_netlist();
/* Get plane layers */
power_plane = get_plane("POWER");
gnd_plane = get_plane("GND");
/* Identify IC locations */
ic_locations = find_components(netlist, type="IC");
/* Place decoupling capacitors */
for each ic in ic_locations:
/* Add multiple vias for low ESL */
cap = add_component(type="Capacitor", value=0.1uF);
add_vias(cap, 3, power_plane, gnd_plane);
/* Distribute smaller value caps nearby */
for i in range(8):
x_offset = random(1, 200);
y_offset = random(1, 200);
cap = add_component(type="Capacitor", value=0.01uF);
move_component(cap, ic.x + x_offset, ic.y + y_offset);
add_vias(cap, 2, power_plane, gnd_plane);
Controlling Resonant Frequencies
The parallel LC circuit formed by parasitic inductance and capacitance can create unintended resonances. At these resonant frequencies, capacitor impedance peaks, losing decoupling effectiveness.
Strategic placement and routing minimizes resonant peaks across operating frequency ranges. Adjusting capacitance and inductance values also enables tuning capacitor networks to avoid noise at sensitive frequencies.
Complex modeling and measurement techniques help designers optimize decoupling performance. Controlled impedance components, like embedded capacitance laminates, provide intrinsically lower inductance for reduced resonances.
Case Studies of Improved Decoupling Performance
One study using high density laminate capacitance layers achieved > 60 dB noise attenuation up to 5 GHz for a test IC. This outperformed traditional decoupling methods by over 10 dB at high frequencies.
Another example replaced multiple surface-mount capacitors with an active embedded decoupling module. The integrated capacitors and inductors smoothed impedances from 500 kHz to over 1.5 GHz. Supply noise decreased by 40%.
In a 2.5D interposer design, high-density trench capacitors fabricated between vertical interconnect layers provided an extremely low inductance charge reservoir. This supported 10 A transient loads with just 50 mV local drop.
