Mosfet Substrate Connections: Why Source And Drain Are Different

Why MOSFET Source and Drain Connections are Asymmetric

Metal-oxide-semiconductor field-effect transistors (MOSFETs) are fundamental building blocks of modern digital integrated circuits. A key property of MOSFET devices is the asymmetry between the source and drain terminals, which enables unidirectional current flow necessary for switching operations.

This article provides an in-depth examination of the physics and engineering considerations that necessitate different electrical connections for the source and drain sides of a MOSFET. We first review semiconductor physics concepts that govern carrier generation and transportation in doped silicon regions. Next, we analyze how tailored doping profiles create inherent asymmetric carrier injection efficiencies between the two terminals. We then use simulation examples to demonstrate how this doping-induced asymmetry directly manifests in the electrical characteristics and performance metrics of MOSFET devices. Finally, we discuss how properly accounting for fundamental source/drain asymmetry allows optimization of modern integrated circuit design and fabrication.

Semiconductor Physics of MOSFET Source and Drain

The source and drain regions in a MOSFET device constitute two terminals between which current flows through the intervening channel area. Both source and drain terminals consist of silicon regions intentionally doped with impurity atoms to increase conductive carrier (electrons or holes) density.

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Doping introduces impurity energy states near the silicon band edges, which shift local Fermi levels. Increased carrier concentration and shifted Fermi levels enable efficient carrier injection into the channel when an external bias is applied between the source and drain.

The key metric governing injection efficiency is the position of the respective Fermi level relative to the conduction/valence band edge. For electrons, n-type doping with shallow donor impurities is used to optimize the source/drain Fermi level alignments. Analogously, p-type doping with acceptors is used to optimize hole injection efficiency in p-channel MOSFETs.

Carrier Generation and Recombination Dynamics

Under applied bias, carrier injection from source/drain terminals into the channel occurs through generation/recombination mechanisms. Thermally generated electron-hole pairs in the depletion region can separate into the source/drain terminals, contributing to the injection current.

Carrier recombination and trap-assisted tunneling across the source/channel or drain/channel energy barriers also enables injection of both majority and minority carriers. However, the rate of these mechanisms depends exponentially on the height of the source/channel or drain/channel barrier – itself controlled by the doping profile.

Carrier Transport to Channel

Once injected into the source or drain terminals, carriers migrate by diffusion and drift processes towards the channel. Drift current arises from the applied electric field while diffusion occurs to reduce spatial carrier density gradients.

Heavily doped source/drain regions with high conductivity lead to efficient carrier transport with minimal resistance losses. Lightly doped extensions provide gentle grading between the channel and source/drain terminals to better match impedances.

Together, the strategic engineering of doping profiles and materials band structure enables optimization of carrier injection rates as well efficient carrier transportation – the key mechanisms governing MOSFET operation.

Doping Concentration Differences Between Source and Drain

With the semiconductor device physics background covered, we now analyze the need for asymmetric doping profiles between the source and drain.

For normal digital switch operation, a MOSFET needs to conduct appreciable current (>100 μA) when turned on in saturation mode, and have a low off-state leakage current (<1 pA) in cut-off. Additionally, fast switching speeds (~1 GHz) with low gate switching energies (<1 fJ) are desirable.

These electrical performance metrics for digital logic applications impose constraints on the allowable doping concentrations on the source and drain sides.

Impact on On-State Current

To achieve high on-state saturation currents, the source injection efficiency into the channel must be maximized. A high source doping concentration brings the Fermi level closer to the conduction band to enable efficient electron injection.

The drain doping can be comparatively lower since carriers have already been accelerated in the channel once they reach the drain. Lower drain doping also increases breakdown voltage allowing higher supply voltages for increased current drive.

Impact on Off-State Leakage

For low off-state leakage, the parasitic reverse-bias diode leakage between the drain and substrate must be minimized. Heavily doped drain regions lead to more band-band and trap-assisted tunneling, increasing leakage.

Reducing drain doping suppresses these leakage paths. The source doping can remain heavy to preserve efficient carrier injection when the FET turns on.

Performance Optimization Goals

Thus, performance optimization requires asymmetric doping profiles – light drain doping to reduce leakage and increase breakdown, while heavy source doping improves on-state current. Typical source/drain doping ratios range from 2:1 to 5:1 in modern high-performance FETs.

In special cases like I/O devices, symmetrical doping may be utilized to meet other voltage/reliability specifications at the cost of switching speed.

Impact of Doping Concentration on Carrier Injection

We will now simulate carrier injection from asymmetrically doped source/drain terminals into the channel to verify the mechanisms governing FET switching performance.

We created 2D Sentaurus TCAD models of a realistic 20nm MOSFET with calibrated doping profiles, material models and boundary conditions. One version has symmetrical medium-doped source/drain regions, while the other has heavily doped source with lightly doped drain.

Band Diagrams and Fermi Levels

The equilibrium electrostatic potential and electron concentrations are plotted below for the two structures with floating terminals:

The heavily doped source in Structure 2 has a high electron concentration which pins the Fermi level close to the conduction band edge. This enables efficient tunneling injection of electrons into the channel. The light drain doping results in a lower electron concentration and larger tunneling barrier height.

Bias-Dependent Carrier Injection

Applying a drain-to-source bias VDS = 2V on both structures shows significantly higher electron injection from the source due to the optimized Fermi level:

Plotting the actual simulated injection current vs. VDS verifies over 2X higher ON current for the asymmetric structure despite the same external bias. This improved current drive is crucial for meeting performance specs.

Thus, tailored asymmetric doping concentrations in the source and drain regions result in optimized carrier injection and conduction, enabling high-performance MOSFET operation.

Example Simulation Code for MOSFET Source/Drain Asymmetry

For readers interested in modeling source/drain asymmetry in MOSFETs, we provide annotated Sentaurus TCAD sample code below. Key steps include:

Import silicon material parameters
Define device geometry and mesh
Introduce dopant species on source/drain with different peak concentrations
Activate dopants and simulate carrier generation
Introduce gate oxide, contacts, and solve electrostatic Poisson equation
Apply bias between terminals and simulate transport equations
Extract terminal currents and carrier densities

###### Import Silicon material properties ######
Material Si = silicon 

###### Define device structure and mesh ######
line x location=0    spacing=2
line y location=0    spacing=2 
init concentration=1e15 field.vacuum 

###### Define Source/Drain regions ######
region source xlo=0 xhi=40 ylo=-30 yhi=0
region drain xlo=0 xhi=40 ylo=0 yhi=30  

doping gaussian phosphorus peak=1e20 space.source\$ 
doping uniform arsenic peak=5e18 space.drain\$   

###### Activate dopants and generate carriers ###### 
physics tmpmob srh auger bgn
solve init
output con.band val.band charge e. mobility 

###### Add Oxide and contacts ######
region gate xlo=0 xhi=40 ylo=-10 yhi=10
interface oxide x.min=0 x.max=40 y.min=-10 y.max=10 

deposit material = SiO2 space.gate$  

contact name=gate workfunction=4.0
contact name=source 
contact name=drain  

solve poisson  

###### Apply bias and simulate transport ######
log outf=mos_iv.log master

solve vd=0 vstep=0.05 vfinal=2 name=drain
solve vd=0 name=source

extract init terminal="drain" maximum y.val from curve="mos_iv.log" get=Id_Vd

###### Plot results ######
tonyplot mos_iv.log  con.band -overlay

With proper calibration, the above framework can provide valuable insights into optimizing doping profiles and biasing strategies for designing high-speed MOS devices and circuits.

Implications for MOSFET Switching Speed and Reliability

In closing, we summarize the key advantages offered by source/drain asymmetry on the performance of state-of-the-art MOSFETs:

2-5X higher ON current drive enables faster charging/discharging of load capacitances
Higher saturation current increases drive strength of digital gates
Lower drain leakage reduces static power dissipation
Higher drain breakdown voltage improves reliability under hot-electron stress
Reduced gate and overlap capacitances allow higher ft and switching speeds

However, overly aggressive asymmetry can also introduce parasitics which compromise performance. Careful numerical process simulation coupled with thorough electrical characterization provides invaluable data for optimizing doping profiles and device dimensions.

Cutting-edge CMOS scaling trends point to novel nanoelectronic architectures with multi-gate and nanopillar channel structures offering ultimate electrostatic integrity. Nevertheless, the fundamental physics driving the need for rational source/drain design will continue playing a pivotal role in Moore’s law well into the foreseeable future.