Understanding Asic Categories: Fpga Conversion Vs. Normal Vs. Full Custom
Defining ASICs and Their Uses
Application-specific integrated circuits (ASICs) are integrated circuits (ICs) customized for a particular use or application rather than intended for general-purpose use. Compared to off-the-shelf ICs, ASICs provide superior performance, lower power consumption, and reduced costs in high-volume production.
The key advantage of an ASIC is that it is customized to precisely match the requirements of a specific application. This customization allows for optimization, reducing unnecessary logic and features that would be present in a general-purpose IC. Some common applications where ASICs provide major benefits include:
- Consumer electronics – e.g. smartphones, tablets
- Networking/telecommunications equipment
- Automotive electronics
- Industrial electronics/Internet of Things (IoT) devices
- Aerospace and defense electronics
There are several categories of ASICs that provide varying levels of customizability and performance:
- FPGA conversion ASICs
- Standard cell ASICs
- Full custom ASICs
The key differences between these categories relate to design methodology, which influences metrics like unit cost, development time, performance, and power efficiency. This article provides an in-depth explanation of each ASIC category.
FPGA Conversion ASICs
FPGA conversion ASICs involve converting a design originally targeted for a field-programmable gate array (FPGA) into an ASIC. This conversion takes the logic designed for the flexible FPGA fabric and implements it in fixed silicon logic for higher performance and lower cost.
Converting FPGA designs to ASIC for lower costs
The motivation for converting an FPGA design into an ASIC is to gain extremely significant cost savings in high-volume production. Building a design in an FPGA first allows rapid prototyping and reduced risk. Once the design is proven, converting to an ASIC reduces the high cost of FPGAs in production runs.
Whereas FPGAs must include universal interconnection resources to support any design, ASIC conversion allows optimizing the design for its specific intended application. Eliminating unused programmable routing resources substantially reduces die area. Since pricing for IC manufacturing is extremely sensitive to die size, this shrinks production costs considerably.
Additional cost savings come from relaxing FPGA timing constraints and power reduction. Optimizing place-and-route for one specific design rather than a flexible FPGA fabric enables much higher performance for the same power. This further reduces chip size/cost.
Example code for a basic FPGA design
Here is a simple example of Verilog code that could be used to design basic digital logic in an FPGA. This code would be a reasonable candidate for conversion to an ASIC once functionality is proven in the FPGA prototype.
// 4-bit binary counter with asynchronous reset
module counter (
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk or posedge reset) begin
if(reset)
count <= 0;
else
count <= count + 1;
end
endmodule
This counter module has a clock input, reset input, and a 4-bit output count. The always block handles the counter logic, incrementing count each clock cycle while reset asynchronously forces count back to 0. After validation in the FPGA, this simple digital design could be migrated to a cheaper ASIC.
Standard Cell ASICs
Standard cell ASICs are constructed by connecting predefined logic gates and circuits together rather than designing full custom layouts. These "standard cells" are low-level logic functions like NAND gates, flip-flops, and adders. Combining these cells by automated place-and-route builds the full IC.
Using predefined cells for faster design
Standard cell design starts with a hardware description language like Verilog or VHDL to specify functionality, then synthesizes this to logic gates. Libraries provide standard cell definitions for each gate, cell, or higher-level block. Automated place-and-route selects physical implementations for each cell and connects them according to the functional design.
The automated flow using predefined standard cells enables much faster design turnaround compared to full custom or FPGA conversion ASICs. The latter rely on manual layout for all logic gates, transistors, and interconnects. Standard cell libraries encapsulate this detailed implementation work, abstracting implementation details from the system designer.
However, standard cells cannot optimize layout perfectly for every possible design. Full custom ASICs can still achieve major power, performance and area improvements over standard cell SoCs for the same functionality. The difference is full custom requires enormous design time investment.
Customization options vs. FPGAs
Even when using predefined standard cells, ASICs provide much more customization and optimization than FPGAs for a fixed design. Standard cell libraries contain a broad variety of logic, memory, clocking, and I/O elements that can be tailored to each design.
FPGAs must maintain uniform structure and delay to support place-and-route across the entire chip. With ASIC standard cells, layout and sizing can optimize timing precisely for just the implemented logic. More complex cells like fast adders also improve efficiency.
So while less flexible than full custom layout, standard cell ASICs still enable significant performance, power and cost improvements vs. FPGAs for mid-to-high volume by customizing for the application.
Full Custom ASICs
In full custom ASIC design, all masks and cell layouts are designed manually rather than relying on predefined standard cells. This fully customized approach is extremely labor and resource intensive but enables the highest level of optimization.
Fully customized layout and design
While standard cell SoCs apply automated place-and-route, full custom ASICs design everything manually. The design team creates schematics and layouts down to the transistor level for the target technology process node. Manual placement of cells and routing of interconnects then integrate these together optimally.
Digitally designing custom mask layers is extremely complex compared to higher-level hardware description languages and standard cells. But the fine-grained control over the entire chip area and ability to tweak designs to perfection supports the highest performance possible.
Highest performance, but more complex
By tailoring entire chips specifically to the target application rather than relying on predefined cells, full custom ASICs maximize speed, efficiency, and density. The lack of overhead circuitry required for flexibility in FPGAs or standard cells also improves efficiency.
For designs like high-speed networking, graphics, and AI accelerators where every last bit of performance matters, full custom ASICs stretch the limits. The same design implemented in a full custom ASIC can easily achieve 2-3x higher maximum clock speeds and throughput versus standard cell.
However, these benefits come at a steep cost. Full custom design complexity slows development cycles to 2-3 years compared to less than one year for standard cell ASICs. Mask and fabrication costs are also much higher for low-volume full custom production runs.
When to choose full custom
Due to the development effort required, full-custom ASICs generally focus on high-value applications justifying $50-100 million-plus total investment. These applications usually have rigid performance, power or form factor constraints where maximum customization provides major competitive advantages.
Some common examples where full custom ASIC development is worthwhile include cryptocurrency mining accelerators, AI inference/training accelerators, 5G base station chips, and other complex SoCs. In these markets pushing the envelope on performance, power and efficiency requires full-custom design.
Full custom can also make sense for relatively low complexity IPs where high volume justifies the mask cost. This includes microcontrollers, sensors, chipsets and other components serving massive end markets.
